Debian Bug report logs - #686949
ITP: fpgatools -- A small independent command line FPGA utilities, no GUI plain C, text-based file formats. convert floorplan from/to bitstream.

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Package: wnpp; Maintainer for wnpp is wnpp@debian.org;

Reported by: Xiangfu Liu <xiangfu@sharism.cc>

Date: Fri, 7 Sep 2012 13:42:01 UTC

Owned by: Xiangfu Liu <xiangfu@openmobilefree.net>

Severity: wishlist

Fixed in version fpgatools/0.0+201212-1

Done: Xiangfu Liu <xiangfu@openmobilefree.net>

Bug is archived. No further changes may be made.

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Report forwarded to debian-bugs-dist@lists.debian.org, debian-devel@lists.debian.org, wnpp@debian.org, Xiangfu Liu <xiangfu@openmobilefree.net>:
Bug#686949; Package wnpp. (Fri, 07 Sep 2012 13:42:04 GMT) Full text and rfc822 format available.

Acknowledgement sent to Xiangfu Liu <xiangfu@sharism.cc>:
New Bug report received and forwarded. Copy sent to debian-devel@lists.debian.org, wnpp@debian.org, Xiangfu Liu <xiangfu@openmobilefree.net>. (Fri, 07 Sep 2012 13:42:04 GMT) Full text and rfc822 format available.

Message #5 received at submit@bugs.debian.org (full text, mbox):

From: Xiangfu Liu <xiangfu@sharism.cc>
To: Debian Bug Tracking System <submit@bugs.debian.org>
Subject: ITP: fpgatools -- A small independent command line FPGA utilities, no GUI plain C, text-based file formats. convert floorplan from/to bitstream.
Date: Fri, 07 Sep 2012 21:37:50 +0800
Package: wnpp
Severity: wishlist
Owner: Xiangfu Liu <xiangfu@openmobilefree.net>

* Package name    : fpgatools
  Version         : 201209
  Upstream Author :  Wolfgang Spraul
* URL             : https://github.com/Wolfgang-Spraul/fpgatools
* License         : UNLICENSE
  Programming Lang: C
  Description     : A small independent command line FPGA utilities, no GUI.
plain C, no C++, text-based file formats. convert floorplan from/to bitstream.



Information forwarded to debian-bugs-dist@lists.debian.org, wnpp@debian.org, Xiangfu Liu <xiangfu@openmobilefree.net>:
Bug#686949; Package wnpp. (Fri, 07 Sep 2012 14:27:03 GMT) Full text and rfc822 format available.

Acknowledgement sent to Timo Juhani Lindfors <timo.lindfors@iki.fi>:
Extra info received and forwarded to list. Copy sent to wnpp@debian.org, Xiangfu Liu <xiangfu@openmobilefree.net>. (Fri, 07 Sep 2012 14:27:03 GMT) Full text and rfc822 format available.

Message #10 received at 686949@bugs.debian.org (full text, mbox):

From: Timo Juhani Lindfors <timo.lindfors@iki.fi>
To: Xiangfu Liu <xiangfu@sharism.cc>
Cc: 686949@bugs.debian.org
Subject: Re: Bug#686949: ITP: fpgatools -- A small independent command line FPGA utilities, no GUI plain C, text-based file formats. convert floorplan from/to bitstream.
Date: Fri, 07 Sep 2012 17:25:18 +0300
Xiangfu Liu <xiangfu@sharism.cc> writes:
>   Description     : A small independent command line FPGA utilities, no GUI.
> plain C, no C++, text-based file formats. convert floorplan from/to
> bitstream.

Sounds interesting but the description is bit generic. What does this
tool let me to do? Are there still non-free tools needed to program FPGA
chips? (I assume yes, it'd be good to document these).





Information forwarded to debian-bugs-dist@lists.debian.org, wnpp@debian.org, Xiangfu Liu <xiangfu@openmobilefree.net>:
Bug#686949; Package wnpp. (Sat, 08 Sep 2012 14:42:03 GMT) Full text and rfc822 format available.

Acknowledgement sent to Xiangfu Liu <xiangfu@sharism.cc>:
Extra info received and forwarded to list. Copy sent to wnpp@debian.org, Xiangfu Liu <xiangfu@openmobilefree.net>. (Sat, 08 Sep 2012 14:42:03 GMT) Full text and rfc822 format available.

Message #15 received at 686949@bugs.debian.org (full text, mbox):

From: Xiangfu Liu <xiangfu@sharism.cc>
To: Timo Juhani Lindfors <timo.lindfors@iki.fi>
Cc: 686949@bugs.debian.org
Subject: Re: Bug#686949: ITP: fpgatools -- A small independent command line FPGA utilities, no GUI plain C, text-based file formats. convert floorplan from/to bitstream.
Date: Sat, 08 Sep 2012 22:38:32 +0800
On 09/07/2012 10:25 PM, Timo Juhani Lindfors wrote:
> Xiangfu Liu <xiangfu@sharism.cc> writes:
>>    Description     : A small independent command line FPGA utilities, no GUI.
>> plain C, no C++, text-based file formats. convert floorplan from/to
>> bitstream.
>
> Sounds interesting but the description is bit generic. What does this

An introduction is on TODO list. :)  it will be using .c files and libfpga
for implement your design.

The author(wolfgang) is working/testing on xilinx slx9 bitstream.

you can take a look at here first.
  https://github.com/Wolfgang-Spraul/fpgatools

> tool let me to do? Are there still non-free tools needed to program FPGA
> chips? (I assume yes, it'd be good to document these).
>

No. no needs non-free tools. maybe other free softwares.

Xiangfu



Information forwarded to debian-bugs-dist@lists.debian.org, wnpp@debian.org, Xiangfu Liu <xiangfu@openmobilefree.net>:
Bug#686949; Package wnpp. (Tue, 11 Sep 2012 08:06:02 GMT) Full text and rfc822 format available.

Acknowledgement sent to Timo Juhani Lindfors <timo.lindfors@iki.fi>:
Extra info received and forwarded to list. Copy sent to wnpp@debian.org, Xiangfu Liu <xiangfu@openmobilefree.net>. (Tue, 11 Sep 2012 08:06:02 GMT) Full text and rfc822 format available.

Message #20 received at 686949@bugs.debian.org (full text, mbox):

From: Timo Juhani Lindfors <timo.lindfors@iki.fi>
To: Xiangfu Liu <xiangfu@sharism.cc>
Cc: 686949@bugs.debian.org
Subject: Re: Bug#686949: ITP: fpgatools -- A small independent command line FPGA utilities, no GUI plain C, text-based file formats. convert floorplan from/to bitstream.
Date: Tue, 11 Sep 2012 11:03:51 +0300
Xiangfu Liu <xiangfu@sharism.cc> writes:
> An introduction is on TODO list. :)  it will be using .c files and libfpga
> for implement your design.
>
> The author(wolfgang) is working/testing on xilinx slx9 bitstream.

I am not very familiar with FPGA concepts since I have not used them yet
so my questions might be bit stupid. I have not used them yet because I
thought they always required non-free tools.

Don't you normally use VHDL or Verilog to describe the models? Is C used
here instead?

> you can take a look at here first.
>   https://github.com/Wolfgang-Spraul/fpgatools

Thanks for the link, I'll pass it on to friends who know about FPGAs :)

-Timo



Information forwarded to debian-bugs-dist@lists.debian.org, wnpp@debian.org, Xiangfu Liu <xiangfu@openmobilefree.net>:
Bug#686949; Package wnpp. (Fri, 14 Sep 2012 12:57:03 GMT) Full text and rfc822 format available.

Acknowledgement sent to "Peter 'p2' De Schrijver" <p2@debian.org>:
Extra info received and forwarded to list. Copy sent to wnpp@debian.org, Xiangfu Liu <xiangfu@openmobilefree.net>. (Fri, 14 Sep 2012 12:57:03 GMT) Full text and rfc822 format available.

Message #25 received at 686949@bugs.debian.org (full text, mbox):

From: "Peter 'p2' De Schrijver" <p2@debian.org>
To: 686949@bugs.debian.org
Subject: place and route
Date: Fri, 14 Sep 2012 15:22:39 +0300
I had a quick look at the tools. They convert a floorplan description into a bitstream
and back. However for a complete workflow the following bits are missing:

* VHDL/verilog compiler to netlist
* place and route tool to turn the netlist into a floorplan

Is this correct?

Thanks,

Peter.



Information forwarded to debian-bugs-dist@lists.debian.org, wnpp@debian.org, Xiangfu Liu <xiangfu@openmobilefree.net>:
Bug#686949; Package wnpp. (Tue, 18 Sep 2012 13:03:09 GMT) Full text and rfc822 format available.

Acknowledgement sent to Timo Juhani Lindfors <timo.lindfors@iki.fi>:
Extra info received and forwarded to list. Copy sent to wnpp@debian.org, Xiangfu Liu <xiangfu@openmobilefree.net>. (Tue, 18 Sep 2012 13:03:09 GMT) Full text and rfc822 format available.

Message #30 received at 686949@bugs.debian.org (full text, mbox):

From: Timo Juhani Lindfors <timo.lindfors@iki.fi>
To: Wolfgang Spraul <wspraul@q-ag.de>
Cc: 686949@bugs.debian.org, "Peter 'p2' De Schrijver" <p2@debian.org>, Xiangfu Liu <xiangfu@sharism.cc>, timo.lindfors@iki.fi
Subject: Re: Bug#686949: ITP: fpgatools -- A small independent command line FPGA utilities, no GUI plain C, text-based file formats. convert floorplan from/to bitstream.
Date: Tue, 18 Sep 2012 16:01:25 +0300
Hi,

> I had a quick look at the tools. They convert a floorplan description
> into a bitstream and back. However for a complete workflow the
> following bits are missing:
>
> * VHDL/verilog compiler to netlist
> * place and route tool to turn the netlist into a floorplan
>
> Is this correct?

Wolfgang, can you comment on this? You can read the full discussion at

http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=686949


best regards,
Timo Lindfors



Information forwarded to debian-bugs-dist@lists.debian.org, wnpp@debian.org, Xiangfu Liu <xiangfu@openmobilefree.net>:
Bug#686949; Package wnpp. (Tue, 18 Sep 2012 23:45:03 GMT) Full text and rfc822 format available.

Acknowledgement sent to Wolfgang Spraul <wspraul@q-ag.de>:
Extra info received and forwarded to list. Copy sent to wnpp@debian.org, Xiangfu Liu <xiangfu@openmobilefree.net>. (Tue, 18 Sep 2012 23:45:03 GMT) Full text and rfc822 format available.

Message #35 received at 686949@bugs.debian.org (full text, mbox):

From: Wolfgang Spraul <wspraul@q-ag.de>
To: Timo Juhani Lindfors <timo.lindfors@iki.fi>
Cc: 686949@bugs.debian.org, Peter 'p2' De Schrijver <p2@debian.org>, Xiangfu Liu <xiangfu@sharism.cc>
Subject: Re: Bug#686949: ITP: fpgatools -- A small independent command line FPGA utilities, no GUI plain C, text-based file formats. convert floorplan from/to bitstream.
Date: Wed, 19 Sep 2012 01:37:13 +0200
Timo,
sure I can and love to comment, thanks for asking.
The state of fpgatools is 'alpha' today, not much is working
yet. But I keep working on it every day. Xiangfu is helping me
with the Debian packaging early because in the past we learned
it sometimes takes years (yes :-)) to make it through all the
various requirements and issues before packages really arrive
in unstable etc. Nothing wrong with high quality but we wanted
to start early this time.

At this moment I am writing the 'hello world' app, which will
be the first simple design that the tools can generate, load
into a xc6slx9 and run there.

> > * VHDL/verilog compiler to netlist
> > * place and route tool to turn the netlist into a floorplan
> >
> > Is this correct?
> 
> Wolfgang, can you comment on this? You can read the full discussion at

I am in the fpga area for a number of years, and numerous tools
exist. fpgatools tries to focus on one of the core missing bits,
which is the bitstream file format.
The way to generate a bitstream right now (as you can see in
the hello world app in a few days), is to link against the libfpga
apis and call apis to fill the chip's resources and routing.
Then instantiate (write) the floorplan/bitstream from memory.

My goal is to make that work really well which will take a few
months. A verilog backend can be added later, but I don't plan
to do that until I have really addressed the chip's features well.
Right now I support maybe 1% of the chip's features...

Most likely the verilog backend would be reactivated in iverilog,
where an 'fpga' target exists but is dormant the last few years.
So my idea was (at that point) to go to iverilog and bring the
fpga target back, and use libfpga in that target to generate
floorplans/bitstreams.

iverilog would then provide a means to program an fpga via
Verilog.
Another potential is that I will first write a small bison
parser as part of fpgatools, then iverilog/verilog later.

So, three steps:

1) program with C api by linking against libfpga to write bitstream
	- you can see how this works in fpgatools' "hello world"
	  app in a few days
2) program with bison-parsed 'new' language that plugs into libfpga
3) program with reactivated iverilog fpga backend

Most likely they will appear in that order, and I will be exclusively
on #1 for at least several more months. If someone wants to join and
start in the iverilog backend today, that would be great of course.

Hope this explains. THANKS FOR ASKING, Cheers,
Wolfgang

On Tue, Sep 18, 2012 at 04:01:25PM +0300, Timo Juhani Lindfors wrote:
> Hi,
> 
> > I had a quick look at the tools. They convert a floorplan description
> > into a bitstream and back. However for a complete workflow the
> > following bits are missing:
> >
> > * VHDL/verilog compiler to netlist
> > * place and route tool to turn the netlist into a floorplan
> >
> > Is this correct?
> 
> Wolfgang, can you comment on this? You can read the full discussion at
> 
> http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=686949
> 
> 
> best regards,
> Timo Lindfors



Information forwarded to debian-bugs-dist@lists.debian.org, wnpp@debian.org:
Bug#686949; Package wnpp. (Thu, 20 Sep 2012 07:48:05 GMT) Full text and rfc822 format available.

Acknowledgement sent to Xiangfu Liu <xiangfu@openmobilefree.net>:
Extra info received and forwarded to list. Copy sent to wnpp@debian.org. (Thu, 20 Sep 2012 07:48:05 GMT) Full text and rfc822 format available.

Message #40 received at 686949@bugs.debian.org (full text, mbox):

From: Xiangfu Liu <xiangfu@openmobilefree.net>
To: Timo Juhani Lindfors <timo.lindfors@iki.fi>, 686949@bugs.debian.org
Subject: Re: Bug#686949: ITP: fpgatools -- tool to program flexible programmable gate arrays.
Date: Thu, 20 Sep 2012 15:46:07 +0800
On 09/11/2012 04:03 PM, Timo Juhani Lindfors wrote:
> I am not very familiar with FPGA concepts since I have not used them yet
> so my questions might be bit stupid. I have not used them yet because I
> thought they always required non-free tools.
> 
> Don't you normally use VHDL or Verilog to describe the models? Is C used
> here instead?

Hi Timo

Using C here. Checkout the source code of hello_world.c:
  https://github.com/Wolfgang-Spraul/fpgatools/blob/master/hello_world.c

>> >   https://github.com/Wolfgang-Spraul/fpgatools
> Thanks for the link, I'll pass it on to friends who know about FPGAs :)

Thanks for that
Xiangfu



Information forwarded to debian-bugs-dist@lists.debian.org, wnpp@debian.org, Xiangfu Liu <xiangfu@openmobilefree.net>:
Bug#686949; Package wnpp. (Thu, 15 Nov 2012 23:00:03 GMT) Full text and rfc822 format available.

Acknowledgement sent to Troy Benjegerdes <hozer@hozed.org>:
Extra info received and forwarded to list. Copy sent to wnpp@debian.org, Xiangfu Liu <xiangfu@openmobilefree.net>. (Thu, 15 Nov 2012 23:00:03 GMT) Full text and rfc822 format available.

Message #45 received at 686949@bugs.debian.org (full text, mbox):

From: Troy Benjegerdes <hozer@hozed.org>
To: 686949@bugs.debian.org
Subject: Re: Bug#686949: ITP: fpgatools -- tool to program flexible programmable gate arrays.
Date: Thu, 15 Nov 2012 16:52:27 -0600
I just wanted to comment that I am extremely excited that there now appears
to be a path to program FPGAs using only DFSG compliant software.

I would also be very interested in figuring out how to add support for
the Xilinx xc3s200a. Where would be the best place to file a feature 
request for this, and/or start documenting what I'd need to do to
implement it myself?

(I ask because I have a couple of these on-order)
http://www.xess.com/prods/prod048.php



Added tag(s) pending. Request was from Anibal Monsalve Salazar <anibal@debian.org> to control@bugs.debian.org. (Tue, 25 Dec 2012 07:06:04 GMT) Full text and rfc822 format available.

Information forwarded to debian-bugs-dist@lists.debian.org, wnpp@debian.org:
Bug#686949; Package wnpp. (Wed, 26 Dec 2012 02:36:05 GMT) Full text and rfc822 format available.

Acknowledgement sent to Xiangfu Liu <xiangfu@openmobilefree.net>:
Extra info received and forwarded to list. Copy sent to wnpp@debian.org. (Wed, 26 Dec 2012 02:36:05 GMT) Full text and rfc822 format available.

Message #52 received at 686949@bugs.debian.org (full text, mbox):

From: Xiangfu Liu <xiangfu@openmobilefree.net>
To: Troy Benjegerdes <hozer@hozed.org>, 686949@bugs.debian.org
Subject: Re: Bug#686949: ITP: fpgatools -- tool to program flexible programmable gate arrays.
Date: Wed, 26 Dec 2012 10:32:28 +0800
On 11/16/2012 06:52 AM, Troy Benjegerdes wrote:
> I just wanted to comment that I am extremely excited that there now appears
> to be a path to program FPGAs using only DFSG compliant software.
> 
> I would also be very interested in figuring out how to add support for
> the Xilinx xc3s200a. Where would be the best place to file a feature 
> request for this, and/or start documenting what I'd need to do to
> implement it myself?

Hi

I think the best will be implement it by yourself. reading the xc3s200a document
and learning the fpgatools structure. then we can merge together easier.

Xiangfu

> 
> (I ask because I have a couple of these on-order)
> http://www.xess.com/prods/prod048.php




Information forwarded to debian-bugs-dist@lists.debian.org, wnpp@debian.org, Xiangfu Liu <xiangfu@openmobilefree.net>:
Bug#686949; Package wnpp. (Wed, 26 Dec 2012 03:48:03 GMT) Full text and rfc822 format available.

Acknowledgement sent to Troy Benjegerdes <hozer@hozed.org>:
Extra info received and forwarded to list. Copy sent to wnpp@debian.org, Xiangfu Liu <xiangfu@openmobilefree.net>. (Wed, 26 Dec 2012 03:48:04 GMT) Full text and rfc822 format available.

Message #57 received at 686949@bugs.debian.org (full text, mbox):

From: Troy Benjegerdes <hozer@hozed.org>
To: Xiangfu Liu <xiangfu@openmobilefree.net>
Cc: 686949@bugs.debian.org
Subject: Re: Bug#686949: ITP: fpgatools -- tool to program flexible programmable gate arrays.
Date: Tue, 25 Dec 2012 21:39:38 -0600
On Wed, Dec 26, 2012 at 10:32:28AM +0800, Xiangfu Liu wrote:
> On 11/16/2012 06:52 AM, Troy Benjegerdes wrote:
> > I just wanted to comment that I am extremely excited that there now appears
> > to be a path to program FPGAs using only DFSG compliant software.
> > 
> > I would also be very interested in figuring out how to add support for
> > the Xilinx xc3s200a. Where would be the best place to file a feature 
> > request for this, and/or start documenting what I'd need to do to
> > implement it myself?
> 
> Hi
> 
> I think the best will be implement it by yourself. reading the xc3s200a document
> and learning the fpgatools structure. then we can merge together easier.
> 
> Xiangfu

Is there a public document on the bitstream format for the xc3s200a? I could
do something with FPGAtools if I had some technical docs on the bitstream
format. 

I could also work on the xc6slx25, (I have a board), but I need something to
work off of to figure out how things are layed out differently between that 
and the lx9.



Reply sent to Xiangfu Liu <xiangfu@openmobilefree.net>:
You have taken responsibility. (Sun, 17 Feb 2013 21:03:08 GMT) Full text and rfc822 format available.

Notification sent to Xiangfu Liu <xiangfu@sharism.cc>:
Bug acknowledged by developer. (Sun, 17 Feb 2013 21:03:08 GMT) Full text and rfc822 format available.

Message #62 received at 686949-close@bugs.debian.org (full text, mbox):

From: Xiangfu Liu <xiangfu@openmobilefree.net>
To: 686949-close@bugs.debian.org
Subject: Bug#686949: fixed in fpgatools 0.0+201212-1
Date: Sun, 17 Feb 2013 21:00:09 +0000
Source: fpgatools
Source-Version: 0.0+201212-1

We believe that the bug you reported is fixed in the latest version of
fpgatools, which is due to be installed in the Debian FTP archive.

A summary of the changes between this version and the previous one is
attached.

Thank you for reporting the bug, which will now be closed.  If you
have further comments please address them to 686949@bugs.debian.org,
and the maintainer will reopen the bug report if appropriate.

Debian distribution maintenance software
pp.
Xiangfu Liu <xiangfu@openmobilefree.net> (supplier of updated fpgatools package)

(This message was generated automatically at their request; if you
believe that there is a problem with it please contact the archive
administrators by mailing ftpmaster@debian.org)


-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Format: 1.8
Date: Tue, 14 Aug 2012 10:03:41 +0800
Source: fpgatools
Binary: libfpga0 libfpga-dev fpgatools
Architecture: source amd64
Version: 0.0+201212-1
Distribution: unstable
Urgency: low
Maintainer: Xiangfu Liu <xiangfu@openmobilefree.net>
Changed-By: Xiangfu Liu <xiangfu@openmobilefree.net>
Description: 
 fpgatools  - tool to program field-programmable gate arrays
 libfpga-dev - development files for fpgatools
 libfpga0   - libraries of fpgatools
Closes: 686949
Changes: 
 fpgatools (0.0+201212-1) unstable; urgency=low
 .
   * New snapshot, taken from commit f4b5b89
   * Initial release. (Closes: #686949)
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Bug archived. Request was from Debbugs Internal Request <owner@bugs.debian.org> to internal_control@bugs.debian.org. (Mon, 18 Mar 2013 07:26:47 GMT) Full text and rfc822 format available.

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Debian bug tracking system administrator <owner@bugs.debian.org>. Last modified: Fri Apr 18 20:43:05 2014; Machine Name: buxtehude.debian.org

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